Tensilica-Cadence Encounter RTL-to-GDSII Methodology Streamlines SoC Design With Diamond Standard Processor Cores
SANTA CLARA, Calif.—(BUSINESS WIRE)—Feb. 21, 2006—
Tensilica(R), Inc., today announced that the company has
worked with Cadence Design Systems, Inc. (Nasdaq:CDNS) to provide
mutual customers with a predictable design path from RTL to first
silicon. The Tensilica-Cadence Encounter(R) RTL-to-GDSII methodology
streamlines the development of SoC designs based on the Tensilica's
new Diamond Standard processor family. The Diamond Standard processor
family includes six cores, ranging from a low-power 32-bit controller
to the industry's highest performance DSP. Tensilica also announced
that it is now a member of Cadence's OpenChoice IP program. The
OpenChoice IP program enables IP interoperability, facilitates
collaboration, and provides access to leading IP providers for Cadence
customers.
The Encounter digital IC design platform integrates global RTL and
physical synthesis, high performance SI-aware routing, and
sophisticated nanometer analysis and optimization. It is ideal for
large scale, low power, yield-sensitive, and other demanding design
challenges and is production-proven through the 65nm node.
"The Encounter platform is a popular RTL-to-GDSII implementation
system for designing low power as well as high performance SoCs. By
supporting Diamond Standard cores based on Tensilica's Xtensa(R)
architecture in this methodology, we give yet another advantage to our
customers to design these cores into their SoCs," stated Eric Filseth,
VP of Product Marketing, Cadence Design Systems. "With this
methodology, our customers should be able to save weeks off their
design cycles."
"Many of our customers use Cadence technology," stated Larry
Przywara, Tensilica's director of strategic alliances. "Our teamwork
with Cadence enables us to provide our mutual customers with a
predictable path from RTL to better first silicon."
About Tensilica
Tensilica offers the broadest line of processor cores on the
market today, with the six new members of the Diamond Standard
processor family plus an infinite number of Xtensa configurable
processor possibilities for customers requiring optimized,
application-specific solutions. Tensilica's low-power,
benchmark-proven processors have been designed into high-volume
products at industry leaders in the digital consumer, networking and
telecommunications markets. Tensilica also provides industry leading
automated tool support for its processor families. For more
information, visit www.tensilica.com.
Editors' Notes:
-- Tensilica and Xtensa are registered trademarks belonging to
Tensilica Inc. First Encounter is a registered trademark and
NanoRoute and CeltIC are trademarks of Cadence Design Systems,
Inc. All other company and product names are trademarks and/or
registered trademarks of their respective owners.
-- Tensilica's announced licensees include Agilent, ALPS, AMCC
(JNI Corporation), Astute Networks, Atheros, ATI, Avision, Bay
Microsystems, Berkeley Wireless Research Center, Broadcom,
Cisco Systems, Conexant Systems, Cypress, Crimson
Microsystems, ETRI, FUJIFILM Microdevices, Fujitsu Ltd.,
Hudson Soft, Hughes Network Systems, Ikanos Communications, LG
Electronics, Marvell, MediaWorks, NEC Laboratories America,
NEC Corporation, NetEffect, Neterion, Nippon Telephone and
Telegraph (NTT), NVIDIA, Olympus Optical Co. Ltd., sci-worx,
Seiko Epson, Solid State Systems, Sony, STMicroelectronics,
Stretch, TranSwitch Corporation, u-Nav Microelectronics, and
Victor Company of Japan (JVC).
Contact:
Tensilica
Paula Jones, 408-327-7343
Email Contact
or
Tanis Communications
Erika Powelson, 831-424-1811
Email Contact
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